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hd404339 series rev. 7.0 sept. 1999 description the hd404339 series is 4-bit hmcs400-series microcomputer with large-capacity memory designed to increase program productivity. each microcomputer has an a/d converter, input capture timer, and a 32- khz oscillator circuit for clock use all built in. they also come with high-voltage i/o pins that can directly drive a fluorescent display. the hd404339 series includes six chips: the hd404339 with 16-kword rom; the hd4043312 with 12- kword rom; the hd404338 with 8-kword rom; the hd404336 with 6-kword rom; the hd404334 with 4-kword rom; the HD4074339 with 16-kword prom. the HD4074339 is a prom version ztat ? microcomputer. programs can be written to the prom by a prom writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (the prom program specifications are the same as for the 27256.) ztat ? : zero turn around time ztat is a trademark of hitachi ltd. features 54 i/o pins ? one input-only pin ? 53 input/output pins: 30 pins are high-voltage pins (40 v, max.) on-chip a/d converter (8-bit 12-channel) three timers ? one event counter input ? one timer output ? one input capture timer 8-bit clock-synchronous serial interface (1 channel) alarm output built-in oscillators ? ceramic or crystal oscillator ? external clock drive is also possible ? subclock: 32.768-khz crystal oscillator
hd404339 series 2 seven interrupt sources ? two by external sources ? three by timers ? one each by the a/d converter and serial interface four low-power dissipation modes ? standby mode ? stop mode ? watch mode ? subactive mode instruction cycle time: 1 m s (f osc = 4 mhz, 1/4 division ratio) ? 1/4, 1/8, 1/16, 1/32 system clock division ratio can be selected ordering information type product name model name rom (words) ram (digit) package mask rom hd404334 hd404334s 4,096 512 dp-64s hd404334fs fp-64b hd404336 hd404336s 6,144 dp-64s hd404336fs fp-64b hd404338 hd404338s 8,912 dp-64s hd404338fs fp-64b hd4043312 hd4043312s 12,288 dp-64s hd4043312fs fp-64b hd404339 hd404339s 16,384 dp-64s hd404339fs fp-64b ztat ? HD4074339 HD4074339s 16,384 dp64s HD4074339fs fp-64b recommended prom programmers and socket adapters prom programmer socket adapter manufacture model name package manufacture model name data i/o corp 121 b dp-64s hitachi hs4339ess01h fp-64b hs4339esf01h aval corp pkw-1000 dp-64s hitachi hs4339ess01h fp-64b hs4339esf01h
hd404339 series 3 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 fp-64b r7 2 r0 0 / sck r0 1 /si r0 2 /so r0 3 /toc test reset osc 1 osc 2 gnd x1 x2 av ss r3 0 /an 0 r3 1 /an 1 r3 2 /an 2 r3 3 /an 3 r4 0 /an 4 r4 1 /an 5 r7 1 r7 0 r6 3 r6 2 r6 1 r6 0 ra 1 /v disp r2 3 r2 2 r2 1 r2 0 r1 3 r1 2 r4 2 /an 6 r4 3 /an 7 r5 0 /an 8 r5 1 /an 9 r5 2 /an 10 r5 3 /an 11 av cc v cc d 0 / int 0 d 1 / int 1 d 2 /evnb d 3 /buzz d 4 / stopc r1 1 r1 0 r9 3 r9 2 r9 1 r9 0 r8 3 r8 2 r8 1 r8 0 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 r6 0 r6 1 r6 2 r6 3 r7 0 r7 1 r7 2 r0 0 / sck r0 1 /si r0 2 /so r0 3 /toc test reset osc 1 osc 2 gnd x1 x2 av ss r3 0 /an 0 r3 1 /an 1 r3 2 /an 2 r3 3 /an 3 r4 0 /an 4 r4 1 /an 5 r4 2 /an 6 r4 3 /an 7 r5 0 /an 8 r5 1 /an 9 r5 2 /an 10 r5 3 /an 11 av cc r8 3 r8 2 r8 1 r8 0 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 / stopc d 3 /buzz d 2 /evnb d 1 / int 1 d 0 / int 0 v cc ra 1 /v disp r2 3 r2 2 r2 1 r2 0 r1 3 r1 2 r1 1 r1 0 r9 3 r9 2 r9 1 r9 0 dp-64s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52
hd404339 series 4 pin description pin number item symbol dp-64s fp-64b i/o function power supply v cc 33 27 applies power voltage gnd 16 10 connected to ground v disp (shared with ra 1 ) 64 58 used as a high-voltage output power supply pin when selected by the mask option test test 12 6 i cannot be used in user applications. connect this pin to gnd. reset reset 13 7 i resets the mcu oscillator osc 1 14 8 i input/output pin for the internal oscillator. connect these pins to the ceramic or crystal oscillator, or osc 1 to an external oscillator circuit. osc 2 15 9 o x1 17 11 i used with a 32.768-khz crystal oscillator for clock purposes x2 18 12 o port d 0 ? 13 34?7 28?1 i/o input/output pins addressed individually by bits; d 0 ? 13 are all high-voltage i/o pins. each pin can be individually configured as selected by the mask option. ra 1 64 58 i one-bit high-voltage input port pin r0 0 ?0 3 , r3 0 ?7 2 1?1, 20?1 1?, 14?5, 59?4 i/o four-bit input/output pins consisting of standard voltage pins r1 0 ?2 3 , r8 0 ?9 3 48?3 42?7 i/o four-bit input/output pins consisting of high voltage pins interrupt int 0 , int 1 34, 35 28, 29 i input pins for external interrupts stop clear stopc 38 32 i input pin for transition from stop mode to active mode serial interface sck 8 2 i/o serial interface clock input/output pin si 9 3 i serial interface receive data input pin so 10 4 o serial interface transmit data output pin timer toc 11 5 o timer output pin evnb 36 30 i event count input pin alarm buzz 37 31 o square waveform output pin
hd404339 series 5 pin number item symbol dp-64s fp-64b i/o function a/d converter av cc 32 26 power supply for the a/d converter. connect this pin as close as possible to the v cc pin and at the same voltage as v cc . if the power supply voltage to be used for the a/d converter is not equal to v cc , connect a 0.1- m f bypass capacitor between the av cc and av ss pins. (however, this is not necessary when the av cc pin is directly connected to the v cc pin.) av ss 19 13 ground for the a/d converter. connect this pin as close as possible to gnd at the same voltage as gnd. an 0 ?n 11 20?1 14?5 i analog input pins for the a/d converter
hd404339 series 6 pin description in prom mode the HD4074339 is a prom version of a ztat ? microcomputer. in prom mode, the mcu stops operating, thus allowing the user to program the on-chip prom. pin number mcu mode prom mode dp-64s fp-64b pin i/o pin i/o 159r6 0 i/o o 4 i/o 260r6 1 i/o o 3 i/o 361r6 2 i/o o 2 i/o 462r6 3 i/o o 1 i/o 563r7 0 i/o o 0 i/o 664r7 1 i/o 71r7 2 i/o 82r0 0 / sck i/o v cc 93r0 1 /si i/o v cc 10 4 r0 2 /so i/o 11 5 r0 3 /toc i/o 12 6 test i v pp 13 7 reset i reset i 14 8 osc 1 iv cc 15 9 osc 2 o 16 10 gnd gnd 17 11 x1 i gnd 18 12 x2 o 19 13 av ss gnd 20 14 r3 0 /an 0 i/o o 0 i/o 21 15 r3 1 /an 1 i/o o 1 i/o 22 16 r3 2 /an 2 i/o o 2 i/o 23 17 r3 3 /an 3 i/o o 3 i/o 24 18 r4 0 /an 4 i/o o 4 i/o 25 19 r4 1 /an 5 i/o o 5 i/o 26 20 r4 2 /an 6 i/o o 6 i/o 27 21 r4 3 /an 7 i/o o 7 i/o 28 22 r5 0 /an 8 i/o 29 23 r5 1 /an 9 i/o 30 24 r5 2 /an 10 i/o
hd404339 series 7 pin number mcu mode prom mode dp-64s fp-64b pin i/o pin i/o 31 25 r5 3 /an 11 i/o 32 26 av cc ? cc 33 27 v cc ? cc 34 28 d 0 / int 0 i/o m 0 i 35 29 d 1 / int 1 i/o m 1 i 36 30 d 2 /evnb i/o a 1 i 37 31 d 3 /buzz i/o a 2 i 38 32 d 4 / stopc i/o 39 33 d 5 i/o a 3 i 40 34 d 6 i/o a 4 i 41 35 d 7 i/o a 9 i 42 36 d 8 i/o v cc 43 37 d 9 i/o 44 38 d 10 i/o 45 39 d 11 i/o 46 40 d 12 i/o 47 41 d 13 i/o 48 42 r8 0 i/o ce i 49 43 r8 1 i/o oe i 50 44 r8 2 i/o a 13 i 51 45 r8 3 i/o a 14 i 52 46 r9 0 i/o 53 47 r9 1 i/o 54 48 r9 2 i/o 55 49 r9 3 i/o 56 50 r1 0 i/o a 5 i 57 51 r1 1 i/o a 6 i 58 52 r1 2 i/o a 7 i 59 53 r1 3 i/o a 8 i 60 54 r2 0 i/o a 0 i 61 55 r2 1 i/o a 10 i 62 56 r2 2 i/o a 11 i 63 57 r2 3 i/o a 12 i 64 58 ra 1 /v disp i notes: 1. i/o: input/output pin; i: input pin; o: output pin 2. o 0 to o 4 consist of two pins each. tie each pair together before using them.
hd404339 series 8 block diagram d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 d 11 d 12 d 13 r0 0 r0 1 r0 2 r0 3 d port r0 port r1 0 r1 1 r1 2 r1 3 r1 port r2 0 r2 1 r2 2 r2 3 r2 port r3 0 r3 1 r3 2 r3 3 r3 port r4 0 r4 1 r4 2 r4 3 r4 port r5 0 r5 1 r5 2 r5 3 r5 port r6 0 r6 1 r6 2 r6 3 r6 port r7 0 r7 1 r7 2 r7 port r8 0 r8 1 r8 2 r8 3 r8 port r9 0 r9 1 r9 2 r9 3 r9 port ra 1 ra port rom (16,384 10 bits) (12,288 10 bits) (8,192 10 bits) pc (14 bits) instruction decoder sp (10 bits) b (4 bits) a (4 bits) st (1 bit) ca (1 bit) alu spy (4 bits) y (4 bits) spx (4 bits) x (4 bits) w (4 bits) ram (512 4 bits) system control interrupt control timer a timer b timer c serial interface a/d converter buzzer internal data bus internal data bus internal address bus buzz av cc an 11 av ss an 0 si so sck toc evnb int 0 int 1 data bus high voltage pin directional signal line gnd v cc x2 x1 osc 2 osc 1 stopc test reset (6,144 10 bits) (4,096 10 bits)
hd404339 series 9 memory map rom memory map vector address area ($0000?000f): reserved for jmpl instructions that branch to the start addresses of the reset and interrupt routines. zero-page subroutine area ($0000?003f): reserved for subroutines. the program branches to a subroutine in this area in response to the cal instruction. pattern area ($0000?0fff): contains rom data that can be referenced with the p instruction. program area ($0000-$0fff (hd404334), $0000-$17ff (hd404336), $0000?1fff (hd404338), $0000?2fff (hd4043312), $0000?3fff (hd404339, HD4074339)): the entire rom area can be used for program coding. $000f $0fff $1000 $2fff $0010 $003f $0040 vector address (16 words) zero-page subroutine (64 words) pattern (4,096 words) hd404334 program (4,096 words) hd404338 program (8,192 words) $0000 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f 0 1 jmpl instruction (jump to reset , stopc routine) jmpl instruction (jump to int routine) jmpl instruction (jump to timer a routine) jmpl instruction (jump to timer b routine) jmpl instruction (jump to timer c routine) jmpl instruction (jump to a/d converter routine) jmpl instruction (jump to int routine) jmpl instruction (jump to serial routine) hd4043312 program (12,288 words) hd404339, HD4074339 program (16,384 words) $1fff $2000 $3000 $3fff hd404336 program (6,144 words) $17ff $1800 note: since the rom address areas between $0000?0fff overlap, the user can determine how these areas are to be used. figure 1 rom memory map
hd404339 series 10 ram memory map a/d channel register (acr) $000 $000 $040 $050 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $020 $023 $033 $034 $035 $036 $037 $00a $00b $00e $00f w w r/w w w w w w w w w w r r r r w r/w r/w r/w r/w r/w $3c0 ram-mapped registers memory registers (mr) stack (64 digits) interrupt control bits area port mode register a (pmra) serial mode register (smr) serial data register lower (srl) serial data register upper (sru) timer mode register a (tma) timer mode register b1 (tmb1) timer b (trbl/twbl) (trbu/twbu) miscellaneous register (mis) timer mode register c (tmc) timer c (trcl/twcl) (trcu/twcu) register flag area port r0 dcr (dcr0) port r3 dcr (dcr3) not used 1. two registers are mapped on the same area ($00a, $00b, $00e, $00f). 2. undefined. timer read register b lower (trbl) timer read register b upper (trbu) timer read register c lower (trcl) timer read register c upper (trcu) timer write register b lower (twbl) timer write register b upper (twbu) timer write register c lower (twcl) timer write register c upper (twcu) r: read only w: write only r/w: read/write $200 notes: $016 r a/d data register lower (adrl) $017 $024 $025 $026 $027 $028 $018 $019 $01a $3ff a/d data register upper (adru) a/d mode register 1 (amr1) a/d mode register 2 (amr2) r w w w port mode register b (pmrb) port mode register c (pmrc) timer mode register b2 (tmb2) system clock selection register 1 (ssr1) not used port r4 dcr (dcr4) port r5 dcr (dcr5) port r6 dcr (dcr6) port r7 dcr (dcr7) w w w w w w w w w $030 data (432 digits) not used system clock selection register 2 (ssr2) not used not used not used 0000 0000 0000 undefined undefined 0000 0000 * 2 /0000 0000 0000 0000 0000 0000 1000 0000 -000 0000 00-0 -000 000- 0000 0000 0000 -000 --00 undefined * 2 /0000 undefined * 1 initial values after reset $03f figure 2 ram memory map and initial values
hd404339 series 11 table 1 initial values of flags after mcu reset item initial value interrupt flags/mask interrupt enable flag (ie) 0 interrupt request flag (if) 0 interrupt mask (im) 1 bit registers watchdog timer on flag (wdon) 0 a/d start flag (adsf) 0 input capture status flag (icsf) 0 input capture error flag (icef) 0 i ad off flag (iaof) 0 ram enable flag (rame) 0 low speed on flag (lson) 0 direct transfer on flag (dton) 0 bit 3 bit 2 bit 1 bit 0 imta (im of timer a) ifta (if of timer a) im1 (im of int 1 ) if1 (if of int 1 ) imtc (im of timer c) iftc (if of timer c) imtb (im of timer b) iftb (if of timer b) ims (im of serial) ifs (if of serial) imad (im of a/d) ifad (if of a/d) $0000 $0001 $0002 $0003 im0 (im of int 0 ) if0 (if of int 0 ) rsp (reset sp bit) ie (interrupt enable flag) icsf (input capture status flag) $020 $021 $022 $023 dton (direct transfer on flag) adsf (a/d start flag) wdon (watchdog on flag) lson (low speed on flag) icef (input capture error flag) rame (ram enable flag) if: interrupt request flag im: interrupt mask ie: interrupt enable flag sp: stack pointer bit 3 bit 2 bit 1 bit 0 ram address iaof (i ad off flag) not used interrupt control bits area register flag area figure 3 interrupt control bits and register flag areas configuration
hd404339 series 12 ie im lson iaof if icsf icef rame rsp wdon adsf dton not used sem/semd not executed allowed allowed rem/remd tm/tmd allowed allowed allowed not executed allowed allowed not executed in active mode used in subactive mode not executed allowed not executed inhibited allowed not executed inhibited inhibited allowed allowed inhibited note: wdon is reset by mcu reset or by stopc enable for stop mode cancellation. the rem or remd instruction must not be executed for adsf during a/d conversion. dton is always reset in active mode. if the tm or tmd instruction is executed for the inhibited bits or non-existing bits, the value in st becomes invalid. figure 4 usage limitations of ram bit manipulation instructions memory registers $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04a $04b $04c $04d $04e $04f $3c0 $3ff mr(0) mr(1) mr(2) mr(3) mr(4) mr(5) mr(6) mr(7) mr(8) mr(9) level 16 level 15 level 14 level 13 level 12 level 11 level 10 level 9 level 8 level 7 level 6 level 5 level 4 level 3 level 2 level 1 mr(10) mr(11) mr(12) mr(13) mr(14) mr(15) pc pc pc pc pc pc pc pc pc pc pc pc st pc ca pc 10 3 13 9 6 2 12 8 5 1 11 7 4 0 bit 3 bit 2 bit 1 bit 0 pc ?c : st: status flag ca: carry flag program counter 13 stack area 0 $3fc $3fd $3fe $3ff figure 5 configuration of memory registers and stack area, and stack position
hd404339 series 13 registers and flags 30 30 30 30 30 30 0 0 0 13 95 1 (b) (a) (w) (x) (y) (spx) (spy) (ca) (st) (pc) (sp) 1111 accumulator b register w register x register y register spx register spy register carry status program counter initial value: 0, no r/w stack pointer initial value: $3ff, no r/w 0 0 initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: 1, no r/w figure 6 registers and flags
hd404339 series 14 addressing modes ram addressing modes register indirect addressing mode: the contents of the w, x, and y registers (10 bits total) are used as a ram address. direct addressing mode: a direct addressing instruction consists of two words. the first word contains the opcode, and the contents of the second word (10 bits) are used as a ram address. memory register addressing mode (lamr, xmra): the memory registers (mr), which are located in 16 addresses from $040 to $04f, are accessed with the lamr and xmra instructions. 0 0 9 9 opcode register indirect addressing 2nd instruction word ram address direct addressing instruction 9 0 0 9 ram address 1st instruction word 3 7 30 memory register addressing 0 9 ram address 000100 opcode instruction 30 30 0 1 w x y figure 7 ram addressing modes
hd404339 series 15 rom addressing modes direct addressing mode: a program can branch to any address in rom memory space by executing the jmpl, brl, or call instruction. current page addressing mode: a program can branch to any address in the current page (256 words per page) by executing the br instruction. zero-page addressing mode: a program can branch to any subroutine located in the zero-page subroutine area ($0000?003f) by executing the cal instruction. table data addressing mode: a program can branch to an address determined by the contents of 4-bit immediate data, the accumulator, and the b register by executing the tbr instruction. 0 0 direct addressing 2nd instruction word program counter current page addressing 97 0 9 program counter 1st instruction word 50 zero-page addressing 00 operand 0 9 table data addressing 7 13 0 9 operand opcode 3 0 13 operand ****** opcode program counter 0 13 3 operand opcode ba 0 9 opcode 00000000 program counter 0 13 figure 8 rom addressing modes
hd404339 series 16 instruction set table 2 instruction set classification instruction type function number of instructions immediate transferring constants to the accumulator, b register, and ram. 4 register-to-register transferring contents of the b, y, spx, spy, or memory registers to the accumulator. 8 ram addressing available when accessing ram in register indirect addressing mode. 13 ram register transferring data between the accumulator and memory. 10 arithmetic performing arithmetic operations with the contents of the accumulator, b register, or memory. 25 compare comparing contents of the accumulator or memory with a constant. 12 ram bit manipulation bit set, bit reset, and bit test. 6 rom addressing branching and jump instructions based on the status condition. 8 input/output controlling the input/output of the r and d ports; rom data reference with the p instruction. 11 control controlling the serial communication interface and low-power dissipation modes. 4 total: 101 instructions
hd404339 series 17 interrupts ie if0 im0 if1 im1 ifta imta iftb imtb iftc imtc ifad imad $000,0 $000,2 $000,3 $001,0 $001,1 $001,2 $001,3 $002,0 $002,1 $002,2 $002,3 $003,0 $003,1 interrupt request priority controller ifs ims $003,2 $003,3 int 0 interrupt int 1 interrupt timer a interrupt timer b interrupt timer c interrupt a/d interrupt serial interrupt priority order vector address 1 2 3 4 5 6 7 $0000 $0002 $0004 $0006 $0008 $000a $000c $000e ( reset , stopc ) figure 9 interrupt control circuit
hd404339 series 18 instruction cycles 123456 instruction execution * interrupt acceptance execution of jmpl instruction at vector address execution of instruction at start address of interrupt routine ie reset vector address generation stacking note: * the stack is accessed and the interrupt enable flag is reset after the instruction is executed, even if it is a two-cycle instruction. figure 10 interrupt processing sequence
hd404339 series 19 operating modes the mcu has five operating modes as shown in table 3. transitions between operating modes are shown in figure 11. table 3 operations in each operating mode function active mode subactive mode standby mode watch mode stop mode system oscillator op stopped op stopped stopped subsystem oscillator op op op op * op cpu op op retained retained reset ram op op retained retained retained timer a op op op op reset timers b, c op op op stopped reset serial op op op stopped reset a/d op stopped op stopped reset i/o op op retained retained reset notes: op implies in operation. * oscillation can be switched on or off with bit 3 of system clock selection register 1 (ssr1: $027).
hd404339 series 20 reset by reset input or by watchdog timer f osc : f x : cpu : clk : per : oscillate oscillate stop f cyc f cyc f osc : f x : cpu : clk : per : oscillate oscillate stop f w f cyc f osc : f x : cpu : clk : per : oscillate oscillate f cyc f cyc f cyc f osc : f x : cpu : clk : per : oscillate oscillate f cyc f w f cyc f osc : f x : cpu : clk : per : stop oscillate f sub f w f sub f osc : f x : cpu : clk : per : stop stop stop stop stop f osc : f x : cpu : clk : per : stop oscillate stop f w stop f osc : f x : cpu : clk : per : stop oscillate stop f w stop standby mode stop mode (tma3 = 0, ssr13 = 1) watch mode subactive mode (tma3 = 1) (tma3 = 1, lson = 0) (tma3 = 1, lson = 1) sby instruction interrupt sby instruction interrupt stop instruction int 0 , timer a f osc : f x : f cyc : f sub : f w : lson: dton: main oscillation frequency subsystem oscillation frequency for time base f osc /4, f osc /8, f osc /16, or f osc /32 (software selectable) f x /8 or f x /4 (software selectable) f x /8 system clock clock for timer a clock for other peripheral functions (except timer a) low speed on flag direct transfer on flag active mode cpu : clk : per : f osc : f x : cpu : clk : per : stop oscillate stop stop stop (tma3 = 0, ssr13 = 0) reset 1 reset 2 rame = 0 rame = 1 int 0 , timer a (tma3 = 0) stop instruction stopc stopc stop instruction 1. stop/sby (dton = 1, lson = 0) 2. stop/sby (dton = 0, lson = 0) 3. stop/sby (dton = don? care, lson = 1) notes: * 1 * 2 * 3 stop instruction figure 11 mcu status transitions
hd404339 series 21 in stop mode, the system oscillator is stopped. to ensure a proper oscillation stabilization period of at least t rc when clearing stop mode, execute the cancellation according to the timing chart in figure 12. in watch and subactive modes, a timer a or int 0 interrupt can be accepted during the interrupt frame period t (see figure 13). note: in watch and subactive modes, an interrupt will not be properly detected if the int 0 high or low level period is shorter than the interrupt frame period t. thus, when operating in watch and subactive modes, maintain the int 0 high or low level period longer than period t to ensure interrupt detection. stop mode oscillator internal clock stop instruction execution t res 3 t rc (stabilization period) t res reset or stopc figure 12 timing of stop mode cancellation active mode interrupt strobe watch mode oscillation stabilization period active mode t t rc t: t : rc interrupt frame length oscillation stabilization period int 0 interrupt request generation (during the transition from watch mode to active mode only) tx t t + t rc t x 2t + t rc figure 13 interrupt frame
hd404339 series 22 the mcu automatically provides an oscillation stabilization period t rc when operation switches from watch mode to active mode. the interrupt frame period t and one of three values for t rc can be selected with the miscellaneous register (mis: $00c), as listed in figure 14. operation can switch directly from subactive mode to active mode, as illustrated in figure 15. in this case, the transition time t d obeys the following relationship. t rc < t d < t + t rc bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 miscellaneous register (mis: $00c) mis1 0 mis0 t * 1 0 0.24414 ms t rc * 1 0.12207 ms 0.24414 ms * 2 7.8125 ms 62.5 ms oscillation circuit conditions external clock input ceramic oscillator 0 1 1 1 0 1 15.625 ms 125 ms not used notes: 1. 2. the values of t and t rc are applied when a 32.768-khz crystal oscillator is used. the value is applied only when direct transfer operation is used. buffer control. refer to figure 24. mis3 mis2 crystal oscillator figure 14 miscellaneous register
hd404339 series 23 subactive mode interrupt strobe direct transfer completion timing mcu internal processing period oscillation stabilization time active mode t t rc t: t : rc stop/sby instruction execution (set lson = 0, dton = 1) interrupt frame period oscillation stabilization time figure 15 direct transition timing mcu operation sequence: the mcu operation flow is shown in figures 16 and 17. reset input is asynchronous, and causes an immediate transition to the reset state from any mpu operation state. the low-power mode operation sequence is shown in figure 17. with the ie flag cleared and an interrupt flag set together with its interrupt mask cleared, if a stop/sby instruction is executed, the instruction is cancelled (regarded as an nop) and the following instruction is executed. before executing a stop/sby instruction, make sure all interrupt flags are cleared or all interrupts are masked.
hd404339 series 24 power on mcu reset rame = 0 ie ? 0 stack ? (pc), (ca), (st) no yes if = 1? reset = 0? sby/stop instruction im = 0 ie = 1 rame = 1 instruction execution reset input pc ? vector address no no no yes yes yes mcu operation cycle pc ? (pc)+1 power-down mode operation cycle (see figure 17) figure 16 mcu operation sequence (power on)
hd404339 series 25 low-power mode operation cycle if = 1 and im = 0? hardware nop execution ? pc next iocation mcu operation cycle standby mode if = 1 and im = 0? hardware nop execution pc next iocation ? instruction execution stop mode no yes no yes stopc = 0? rame = 1 reset mcu no yes figure 17 mcu operating sequence (low-power mode operation)
hd404339 series 26 oscillator circuit figure 18 shows a block diagram of the clock generation circuit. the system clock frequency of the oscillator connected to osc 1 and osc 2 can be selected by system clock selection registers 1 and 2 (ssr1, 2: $027, $028) as shown in figures 20 and 21. the system clock division ratio can be set by software to be 1/4, 1/8, 1/16, or 1/32. the subsystem clock division ratio can be set by software to be 1/4 or 1/8. osc 2 osc 1 x1 x2 system oscillator sub- system oscillator 1/4, 1/8, 1/16, or 1/32 division circuit timing generator circuit system clock selection cpu with rom, ram, registers, flags, and i/o peripheral function interrupt time-base interrupt time-base clock selection 1/8 or 1/4 division circuit timing generator circuit timing generator circuit 1/8 division circuit f w f sub t subcyc lson tma3 f cyc t cyc f osc f x t wcyc cpu per clk notes: 1. 2. the system clock division ratio can be selected by setting bit 1 or 0 of the system clock select register 2 (ssr2: $028). the system clock division ratio can be selected by setting bit 2 of the system clock select register 1 (ssr1: $027). * 1 * 2 figure 18 clock generation circuit
hd404339 series 27 osc 2 x1 gnd osc 1 rese t x2 av ss gnd figure 19 typical layout of crystal and ceramic oscillators
hd404339 series 28 table 4 oscillator circuit examples circuit configuration circuit constants external clock operation external oscillator osc open 1 osc 2 ceramic oscillator (osc 1 , osc 2 ) osc 2 c 1 2 c osc 1 r f ceramic gnd ceramic oscillator: csa4.00mg (murata) r f = 1 m w 20% c 1 = c 2 = 30 pf 20% crystal oscillator (osc 1 , osc 2 ) osc 2 c 1 2 c osc 1 r f crystal gnd l s c r s c 0 osc 1 osc 2 r f = 1 m w 20% c 1 = c 2 = 10 to 22 pf 20% crystal: equivalent to circuit shown below c 0 = 7 pf max. r s = 100 w max. crystal oscillator (x1, x2) x1 c 1 2 c x2 crystal gnd l s c r s c 0 x1 x2 crystal: 32.768 khz: mx38t (nippon denpa) c 1 = c 2 = 20 pf 20% r s = 14 k w c 0 = 1.5 pf notes: 1. since the circuit constants change depending on the crystal or ceramic oscillator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. wiring among osc 1 , osc 2 , x1, x2 and elements should be as short as possible, and must not cross other wiring (see figure 19). 3. when a 32.768-khz crystal oscillator is not used, fix pin x1 to gnd and leave pin x2 open.
hd404339 series 29 bit initial value read/write bit name 3 0 w ssr13 * 1 2 0 w ssr12 0 not used 1 0 w ssr11 system clock selection register 1 (ssr1: $027) system clock selection * 2 0.4 to 1.0 mhz 1.6 to 4.5 mhz ssr11 0 1 ssr12 0 1 ratio selection f sub = f x /8 f sub = f x /4 32-khz oscillation division ssr13 0 1 32-khz oscillation stop oscillation operates in stop mode oscillation stops in stop mode notes: * 1 * 2 ssr13 will only be cleared to 0 by a reset input. a stopc input during stop mode will not clear ssr13. also note that ssr13 will not be cleared upon transition to stop mode. when the subsystem oscillator (32.768 khz crystal oscillator) is used, set 0.4 mhz f osc 1.0mhz or 1.6 mhz f osc 4.5 mhz. figure 20 system clock selection register 1 (ssr1) bit initial value read/write bit name 3 not used 2 not used 0 0 w ssr20 1 0 w ssr21 system clock selection register 2 (ssr2: $028) ssr21 0 0 1 1 ssr20 0 1 0 1 system clock division ratio 1/4 division 1/8 division 1/16 division 1/32 division figure 21 system clock selection register 2 (ssr2)
hd404339 series 30 i/o ports the mcu has 53 input/output pins (d 0 ? 13 , r0 0 ?9 3 ) and one input-only pin (ra 1 ). the 30 pins consisting of ports d 0 ? 13 , r1, r2, r8, and r9 are all high-voltage i/o pins. ra 1 is a high- voltage input-only pin. the high-voltage pins can be equipped with or without pull-down resistance, as selected by the mask option. all standard voltage output pins are cmos output pins. however, the r0 2 /so pin can be programmed for nmos open-drain output. in stop mode, input/output pins go to the high-impedance state. all standard voltage input/output pins have pull-up mos built in, which can be individually turned on or off by software (table 5). pull-up mos on/off settings can be made independently of settings as on-chip supporting module pins. table 5 control of standard i/o pins by program mis3 (bit 3 of mis) 0 1 dcr 01 01 pdr 0101 0101 cmos buffer pmos ?n?n nmos on on pull-up mos ?non note: ?indicates off.
hd404339 series 31 bit initial value read/write bit name 3 0 w dcr03, 2 0 w dcr02, 0 0 w dcr00, 1 0 w dcr01, dcr0, dcr3 to dcr7 data control register (dcr0: $030, dcr3 to dcr7: $033 to $037) dcr33 to dcr63 dcr32 to dcr72 dcr30 to dcr70 dcr31 to dcr71 bits 0 to 3 0 cmos buffer control cmos buffer off (high impedance) cmos buffer on register dcr0 dcr3 dcr4 dcr5 dcr6 dcr7 bit 3 r0 3 r3 3 r4 3 r5 3 r6 3 not used correspondence between ports and dcr bits bit 2 r0 2 r3 2 r4 2 r5 2 r6 2 r7 2 bit 1 r0 1 r3 1 r4 1 r5 1 r6 1 r7 1 bit 0 r0 0 r3 0 r4 0 r5 0 r6 0 r7 0 1 figure 22 data control register (dcr)
hd404339 series 32 table 6 circuit configurations of standard i/o pins i/o pin type circuit pins input/output pins v cc v cc pull-up control signal buffer control signal output data input data hlt mis3 pdr input control signal dcr r0 0 , r0 1 , r0 3 , r3 0 ?3 3 , r4 0 ?4 3 , r5 0 ?5 3 , r6 0 ?6 3 , r7 0 ?7 2 v cc v cc pull-up control signal buffer control signal output data input data hlt mis3 dcr pdr input control signal mis2 r0 2 peripheral function pins input/ output pins v cc v cc pull-up control signal output data input data hlt mis3 sck sck sck output pins v cc v cc pull-up control signal pmos control signal output data hlt mis3 so mis2 so v cc v cc pull-up control signal output data hlt mis3 toc toc
hd404339 series 33 i/o pin type circuit pins peripheral function pins input/ pins v cc input data hlt mis3 si pdr si input control v cc hlt mis3 pdr a/d input an 0 ?n 11 notes: 1. in stop mode, the mcu is reset and the peripheral function selection is cancelled. the hlt signal goes low, and input/output pins enter the high-impedance state. 2. the hlt signal is 1 in active, standby, watch, and subactive modes. table 7 circuit configurations for high-voltage input/output pins i/o pin type with pull-down resistance without pull-down resistance pins input/output pins v cc input data input control signal hlt output data v disp pull-down resistance v cc input data input control signal output data hlt d 0 ? 13 , r1 0 ?1 3 , r2 0 ?2 3 , r8 0 ?8 3 , r9 0 ?9 3 input pins input data input control signal ra 1 peripheral function pins output pins v cc output data v disp pull-down resistance hlt v cc output data hlt buzz input pins input data pull-down resistance v disp input data int 0 , int 1 , evnb, stopc note: hlt goes high in active, standby, watch, and subactive modes.
hd404339 series 34 bit initial value read/write bit name 3 0 w pmra3 2 0 w pmra2 0 0 w pmra0 1 0 w pmra1 pmra0 0 1 r0 2 /so mode selection r0 2 so port mode register a (pmra: $004) pmra1 0 1 r0 1 /si mode selection r0 1 si pmra2 0 1 r0 3 /toc mode selection r0 3 toc pmra3 0 1 d 3 /buzz mode selection d 3 buzz figure 23 port mode register a (pmra) bit initial value read/write bit name 3 0 w pmrb3 2 0 w pmrb2 0 0 w pmrb0 1 0 w pmrb1 pmrb0 0 1 d 0 / int 0 mode selection d 0 int 0 port mode register b (pmrb: $024) pmrb1 0 1 d 1 / int 1 mode selection d 1 int 1 pmrb2 0 1 d 2 /evnb mode selection d 2 evnb pmrb3 0 1 d 4 / stopc mode selection d 4 stopc * note: pmrb3 is reset to 0 only by reset input. when stopc is input in stop mode, pmrb3 is not reset but retains its value. * figure 24 port mode register b (pmrb)
hd404339 series 35 bit initial value read/write bit name 3 0 w mis3 2 0 w mis2 0 0 w mis0 1 0 w mis1 mis2 cmos buffer on/off selection for pin r0 2 /so miscellaneous register (mis: $00c) 0 1 cmos on cmos off refer to figure 14 in the operation modes section. t rc selection. mis3 0 1 pull-up mos on/off selection pull-up mos off pull-up mos on (refer to table 5) mis1 mis0 note: the on/off status of each transistor and the peripheral function mode of each pin can be set independently. figure 25 miscellaneous register
hd404339 series 36 prescaler the mcu has two built-in prescalers, s and w (pss, psw). they divide the system clock and subsystem clock, and output these divided clocks to the peripheral function modules, as shown in figure 26. subsystem clock prescaler w timer a timer b timer c serial system clock prescaler s clock selector f x /8 f x /4 or f x /8 figure 26 prescaler output supply
hd404339 series 37 timers the mcu has three built-in timers a, b, and c. the functions of each timer are listed in table 7. timer a timer a is an 8-bit free-running timer that can also be used as a clock time-base with a 32.768-khz subsystem oscillator. timer a has the following features: one of eight internal clocks can be selected from prescaler s according to the setting of timer mode register a (tma: $008) in time-base mode, one of five internal clocks can be selected from prescaler w according to the setting of timer mode register a an interrupt request can be generated when timer counter a (tca) overflows input clock frequency must not be modified during timer a operation table 7 timer functions functions timer a timer b timer c clock source prescaler s available available available prescaler w available external event available timer functions free-running available available available time base available event counter available reload available available watchdog available input capture available timer output pwm available
hd404339 series 38 1/4 1/2 32.768-khz oscillator system clock prescaler w (psw) selector selector prescaler s (pss) selector internal data bus timer a interrupt request flag (ifta) clock overflow timer counter a (tca) timer mode register a (tma) 3 2 f 1/2 t wcyc f t wcyc per 2 4 8 32 128 512 1024 2048 ? ? ? ? ? ? ? ? 2 8 16 32 ? ? ? ? w w figure 27 timer a block diagram
hd404339 series 39 bit initial value read/write bit name 3 0 w tma3 2 0 w tma2 0 0 w tma0 1 0 w tma1 timer mode register a (tma: $008) 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 pss pss pss pss pss pss pss pss psw psw psw psw psw operating mode timer a mode tma3 tma1 tma2 tma0 source prescaler 2048 t cyc 1024 t cyc 512 t cyc 128 t cyc 32 t cyc 8 t cyc 4 t cyc 2 t cyc input clock frequency 0 1 1 32t 16t 8t 2t 1/2t time-base mode 0 0 1 1 0 1 1 not used psw and tca reset x notes: wcyc wcyc wcyc wcyc wcyc x = don? care. 1. 2. 3. t = 244.14 s (when a 32.768-khz crystal oscillator is used) timer counter overflow output period (seconds) = input clock period (seconds) 256. the division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. wcyc figure 28 timer mode register a (tma)
hd404339 series 40 timer b timer b is an 8-bit multifunction timer that includes free-running, reload, and input capture timer features. these are described as follows. by setting timer mode register b1 (tmb1: $009), one of seven internal clocks supplied from prescaler s can be selected, or timer b can be used as an external event counter by setting timer mode register b2 (tmb2: $026), detection edge type of evnb can be selected. by setting timer write register bl, u (twbl, u: $00a, $00b), timer counter b (tcb) can be written to during reload timer operation by setting timer read register bl, u (trbl, u: $00a, $00b), the contents of timer counter b can be read out timer b can be used as an input capture timer to count the clock cycles between trigger edges input as an external event an interrupt can be requested when timer counter b overflows or when a trigger input edge is received during input capture operation
hd404339 series 41 timer counter b (tcb) timer mode register b2 (tmb2) evnb selector system clock per prescaler s (pss) 2 edge detector edge detection control signal 3 timer write register b lower (twbl) timer mode register b1 (tmb1) timer write register b upper (twbu) clock free-running timer control signal timer read register b lower (trbl) interrupt request flag of timer b (iftb) timer read register bu (trbu) overflow internal data bus 2 4 8 32 128 512 2048 ? ? ? ? ? ? ? figure 29 timer b free-running and reload operation block diagram
hd404339 series 42 timer counter b (tcb) internal data bus timer mode register b2 (tmb2) evnb selector system clock per prescaler s (pss) 2 edge detector edge detection control signal 3 timer mode register b1 (tmb1) clock input capture timer control signal timer read register b lower (trbl) interrupt request flag of timer b (iftb) timer read register bu (trbu) overflow read signal input capture status flag (icsf) input capture error flag (icef) error controller 2 4 8 32 128 512 2048 ? ? ? ? ? ? ? figure 30 timer b input capture operation block diagram
hd404339 series 43 bit initial value read/write bit name 3 0 w tmb13 2 0 w tmb12 0 0 w tmb10 1 0 w tmb11 timer mode register b1 (tmb1: $009) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmb12 tmb10 tmb11 input clock period and input clock source d 2 /evnb (external event input) tmb13 0 1 free-running/reload timer selection free-running timer reload timer figure 31 timer mode register b1 (tmb1) bit initial value read/write bit name 3 not used 2 0 w tmb22 0 0 w tmb20 1 0 w tmb21 timer mode register b2 (tmb2: $026) tmb21 0 1 tmb20 0 1 0 1 evnb edge detection selection no detection falling edge detection rising edge detection rising and falling edge detection tmb22 0 1 free-running/reload and input capture selection free-running/reload input capture figure 32 timer mode register b2 (tmb2)
hd404339 series 44 timer c timer c is an 8-bit multifunction timer that includes free-running, reload, and watchdog timer features, which are described as follows. by setting timer mode register c (tmc: $00d), one of eight internal clocks supplied from prescaler s can be selected by selecting pin toc with bit 2 (pmra2) of port mode register a (pmra: $004), timer c output (pwm output) is enabled by setting timer write register cl, u (twcl, u: $00e, $00f), timer counter c (tcc) can be written to by setting timer read register cl, u (trcl, u: $00e, $00f), the contents of timer counter c can be read out an interrupt can be requested when timer counter c overflows timer counter c can be used as a watchdog timer for detecting runaway programs
hd404339 series 45 timer counter c (tcc) port mode register a (pmra) selector system clock per prescaler s (pss) 3 timer write register c lower (twcl) timer mode register c (tmc) timer write register c upper (twcu) clock free-running timer control signal timer read register c lower (trcl) interrupt request flag of timer c (iftc) timer read register cu (trcu) overflow toc timer output control signal watchdog timer controller watchdog on flag (wdon) system reset signal internal data bus timer output control logic 2 4 8 32 128 512 1024 2048 ? ? ? ? ? ? ? ? figure 33 timer c block diagram
hd404339 series 46 bit initial value read/write bit name 3 0 w tmc3 2 0 w tmc2 0 0 w tmc0 1 0 w tmc1 timer mode register c (tmc: $00d) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2048t cyc 512t cyc 128t cyc 32t cyc 8t cyc 4t cyc 2t cyc tmc2 tmc0 tmc1 input clock period tmc3 0 1 free-running/reload timer selection free-running timer reload timer 1024t cyc figure 34 timer mode register c (tmc) $ff + 1 $00 timer c count value overflow time cpu operation normal operation timer c clear normal operation timer c clear program runaway normal operation reset figure 35 watchdog timer operation flowchart
hd404339 series 47 t (n + 1) t 256 t t (256 ?n) tmc3 = 0 (free-running timer) tmc3 = 1 (reload timer) notes: t: input clock period supplied to counter. (the clock source and system clock division ratio are determined by timer mode register c.) n: value of timer write register c. (when n = 255 ($ff), pwm output is fixed low.) figure 36 pwm output waveform
hd404339 series 48 notes on use when using the timer output as pwm output, note the following point. from the update of the timer write register until the occurrence of the overflow interrupt, the pwm output differs from the period and duty settings, as shown in table 8. the pwm output should therefore not be used until after the overflow interrupt following the update of the timer write register. after the overflow, the pwm output will have the set period and duty cycle. table 8 pwm output following update of timer write register pwm output mode timer write register is updated during high pwm output timer write register is updated during low pwm output free running timer write register updated to value n interrupt request t (255 ?n) t (n + 1) timer write register updated to value n interrupt request t (n' + 1) t (255 ?n) t (n + 1) reload timer write register updated to value n interrupt request t t (255 ?n) t timer write register updated to value n interrupt request t t (255 ?n) t
hd404339 series 49 alarm output function the mcu has an alarm output function built in. by setting port mode register c (pmrc: $025), one of four alarm frequencies supplied from the pss can be selected. internal data bus selector system clock per prescaler s (pss) 2 alarm output control signal buzz alarm output controller port mode register c (pmrc) port mode register a (pmra) ? ? ? ? 256 512 1024 2048 figure 37 alarm output function block diagram table 9 port mode register c pmrc bit 3 bit 2 system clock divisor 00 ? 2048 1 ? 1024 10 ? 512 1 ? 256
hd404339 series 50 serial interface the mcu has a one-channel serial interface built in with the following features. one of 13 different internal clocks or an external clock can be selected as the transmit clock. the internal clocks include the six prescaler outputs divided by two and by four, and the system clock. during idle status, the serial output pin can be controlled to be high or low output transmit clock errors can be detected an interrupt request can be generated after transfer has completed when an error occurs internal data bus port mode register c (pmrc) sck selector system clock per prescaler s (pss) idle controller 3 serial mode register (smr) clock serial data register (sr) serial interrupt request flag (ifs) selector 1/2 1/2 si so octal counter (oc) i/o controller transfer control signal 2 8 32 128 512 2048 ? ? ? ? ? ? figure 38 serial interface block diagram
hd404339 series 51 table 10 serial interface operating modes smr pmra bit 3 bit 1 bit 0 operating mode 1 0 0 continuous clock output mode 1 transmit mode 1 0 receive mode 1 transmit/receive mode sts wait state (octal counter = 000, transmit clock disabled) transmit clock wait state (octal counter = 000) transfer state (octal counter = 000) mcu reset smr write sts instruction transmit clock 8 transmit clocks or sts instruction (ifs 1) ? smr write (ifs 1) ? external clock mode sts wait state (octal counter = 000, transmit clock disabled) transmit clock wait state (octal counter = 000) transfer state (octal counter = 000) smr write sts instruction transmit clock sts instruction (ifs 1) ? 8 transmit clocks or internal clock mode continuous clock output state (pmra 0, 1 = 00) smr write transmit clock mcu reset ? smr write (ifs 1) figure 39 serial interface state transitions
hd404339 series 52 lsb msb 12 345 678 transmit clock serial output data serial input data latch timing figure 40 serial interface timing
hd404339 series 53
state mcu reset pmra write smr write pmrc write sck pin sts wait state transmit clock wait state transfer state transmit clock wait state sts wait state port selection external clock selection output level control in idle states dummy write for state transition output level control in idle states data write for transmission undefined lsb msb flag reset at transfer completion external clock mode state mcu reset pmra write smr write pmrc write sts wait state transfer state transmit clock wait state sts wait state port selection internal clock selection output level control in idle states data write for transmission output level control in idle states undefined lsb msb flag reset at transfer completion internal clock mode (input) instruction write srl, sru sts so pin ifs sck pin (output) instruction write srl, sru sts so pin ifs figure 41 example of serial interface operation sequence
hd404339 series 54 transmit clock errors are detected as illustrated in figure 42. transfer completion (ifs 1) interrupts inhibited ifs 0 smr write ifs = 1 transmit clock error processing normal termination ? ? yes no transmit clock error detection flowchart transmit clock error detection procedure state sck pin (input) transmit clock wait state transfer state transfer state transmit clock wait state noise transfer state has been entered by the transmit clock error. when smr is written, ifs is set. flag set because octal counter reaches 000. flag reset at transfer completion. smr write ifs 12 3 45678 figure 42 transmit clock error detection
hd404339 series 55 table 11 transmit clock selection pmrc smr bit 0 bit 2 bit 1 bit 0 system clock divisor transmit clock frequency 0000 ? 2048 4096t cyc 1 ? 512 1024t cyc 10 ? 128 256t cyc 1 ? 32 64t cyc 100 ? 8 16t cyc 1 ? 24t cyc 1000 ? 4096 8192t cyc 1 ? 1024 2048t cyc 10 ? 256 512t cyc 1 ? 64 128t cyc 100 ? 16 32t cyc 1 ? 48t cyc bit initial value read/write bit name 3 0 w smr3 2 0 w smr2 0 0 w smr0 1 0 w smr1 serial mode register (smr: $005) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 smr2 smr0 smr1 smr3 0 1 r0 0 / sck mode selection r0 0 sck sck output output input clock source external clock prescaler division ratio refer to table 11 prescaler system clock figure 43 serial mode register (smr)
hd404339 series 56 bit initial value read/write bit name 3 0 w pmrc3 2 0 w pmrc2 0 0 w pmrc0 1 undefined w pmrc1 port mode register c (pmrc: $025) pmrc1 0 1 output level control in idle states low level high level pmrc0 0 1 serial clock division ratio prescaler output divided by 2 prescaler output divided by 4 alarm output function. refer to table 9. figure 44 port mode register c (pmrc)
hd404339 series 57 a/d converter the mcu also contains a built-in a/d converter that uses a sequential comparison method with a resistance ladder. it can perform digital conversion of twelve analog inputs with 8-bit resolution. the following describes the a/d converter. a/d mode register 1 (amr1: $019) is used to select digital or analog ports a/d mode register 2 (amr2: $01a) is used to set the a/d conversion speed and to select digital or analog ports the a/d channel register (acr: $016) is used to select an analog input channel a/d conversion is started by setting the a/d start flag (adsf: $020, 2) to 1. after the conversion is completed, converted data is stored in the a/d data register, and at the same time the a/d start flag is cleared to 0. by setting the i ad off flag (iaof: $021, 2) to 1, the current flowing through the resistance ladder can be cut off even while operating in standby or active mode the a/d data register is a read-only register consisting of a lower 4 bits and upper 4 bits (adrl: $017, adru: $018). this register is not cleared by a reset. data reads during a/d conversion are not guaranteed. after a/d conversion ends, the resultant 8-bit data is set in this register and held until the start of the next conversion (figures 51 to 53).
hd404339 series 58 i ad off flag (iaof) selector 4 a/d channel register (acr) a/d mode register 2 (amr2) a/d mode register 1 (amr1) a/d interrupt request flag (ifad) encoder a/d data register (adru, l) a/d start flag (adsf) operating mode signal (1 in stop, watch, and subactive modes) internal data bus + comp a/d controller an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 an 8 an 9 an 10 an 11 control signal for conversion time 4 2 d/a av cc av ss figure 45 a/d converter block diagram
hd404339 series 59 notes on usage use the sem or semd instruction for writing to the a/d start flag (adsf) do not write to the a/d start flag during a/d conversion data in the a/d data register during a/d conversion is undefined since the operation of the a/d converter is based on the clock from the system oscillator, the a/d converter does not operate in stop, watch, or subactive mode. in addition, to save power while in these modes, all current flowing through the converter? resistance ladder is cut off. if the power supply for the a/d converter is to be different from v cc , connect a 0.1- m f bypass capacitor between the av cc and av ss pins. (however, this is not necessary when the av cc pin is directly connected to the v cc pin.) the port data register (pdr) is initialized to 1 by an mcu reset. at this time, if pull-up mos is selected as active by bit 3 of the miscellaneous register (mis3), the port will be pulled up to v cc . when using a shared r port/analog input pin as an input pin, clear pdr to 0. otherwise, if pull-up mos is selected by mis3 and pdr is set to 1, a pin selected by bit 1 of the a/d mode registr as an analog pin will remain pulled up. bit initial value read/write bit name 3 0 w amr13 2 0 w amr12 0 0 w amr10 1 0 w amr11 amr10 0 1 an 0 a/d mode register 1 (amr1: $019) amr11 0 1 an 1 amr12 0 1 r3 2 /an 2 mode selection r3 2 an 2 amr13 0 1 r3 3 /an 3 mode selection r3 3 an 3 r3 0 /an 0 mode selection r3 0 r3 1 /an 1 mode selection r3 1 figure 46 a/d mode register 1 (amr1)
hd404339 series 60 bit initial value read/write bit name 3 not used 2 0 w amr22 0 0 w amr20 1 0 w amr21 amr20 0 1 67 t cyc a/d mode register 2 (amr2: $01a) amr21 0 1 an 4 ?n 7 amr22 0 1 r5/an 8 ?n 11 pin selection r5 an 8 ?n 11 conversion time 34 t cyc r4/an 4 ?n 7 pin selection r4 figure 47 a/d mode register 2 (amr2)
hd404339 series 61 bit initial value read/write bit name 3 0 w acr3 2 0 w acr2 0 0 w acr0 1 0 w acr1 a/d channel register (acr: $016) 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 don? care analog input selection an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 an 8 an 9 an 10 an 11 not used acr3 acr1 acr2 acr0 0 1 1 0 0 1 1 don? care 1 figure 48 a/d channel register (acr)
hd404339 series 62 bit initial value read/write bit name 3 0 r/w dton 2 0 r/w adsf 0 0 r/w lson 1 0 w wdon a/d start flag (adsf: $020, bit 2) refer to the description of operating modes dton refer to the description of timers wdon refer to the description of operating modes lson 0 1 a/d conversion completed a/d conversion started a/d start flag (adsf) figure 49 a/d start flag (adsf) bit initial value read/write bit name 3 0 r/w rame 2 0 r/w iaof 0 0 r/w icsf 1 0 r/w icef i ad off flag (iaof: $021, bit 2) refer to the description of operating modes rame refer to the description of timers icef refer to the description of timers icsf 0 1 i ad current flows i ad current is cut off i ad off flag (iaof) figure 50 i ad off flag (iaof)
hd404339 series 63 msb bit 7 lsb bit 0 result 0 1 adrl: $017 2 3 0 1 adru: $018 2 3 figure 51 a/d data register 0 r 0 adrl0 1 r 0 adrl1 bit read/write initial value after reset bit name a/d data register (lower) (adrl: $017) 2 r 0 adrl2 3 r 0 adrl3 figure 52 a/d data register (lower) (adrl) 0 r 0 adru0 1 r 0 adru1 bit read/write initial value after reset bit name a/d data register (upper) (adru: $018) 2 r 0 adru2 3 r 1 adru3 figure 53 a/d data register (upper) (adru)
hd404339 series 64 notes on mounting assemble all parts including the hd404339 series on a board, noting the points described below. 1. connect layered ceramic type capacitors (about 0.1 m f) between av cc and av ss , between v cc and gnd, and between used analog pins and av ss . 2. connect unused analog pins to av ss .
hd404339 series 65 av an an to an av cc ss 0 1 11 av an an an to an av cc ss 0 1 2 11 av an an an to an av cc ss 0 1 2 11 1. when not using an a/d converter. v gnd cc v gnd cc v gnd cc 2. when using pins an and an but not using an to an . 01 211 3. when using all analog pins. 0.1 f 3 0.1 f 13 0.1 f figure 54 example of connections (av cc to av ss ) between the v cc and gnd lines, connect capacitors designed for use in ordinary power supply circuits. an example connection is described in figure 54. no resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in parallel. the capacitors are a large capacitance c 1 and a small capacitance c 2 .
hd404339 series 66 v gnd cc v gnd cc c 1 c 2 figure 55 example of connections (v cc to gnd)
hd404339 series 67 absolute maximum ratings item symbol value unit notes supply voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +14.0 v 1 pin voltage v t ?.3 to v cc + 0.3 v 2 v cc ?45 to v cc + 0.3 v 3 total permissible input current ? i o 70 ma 4 total permissible output current ? i o 150 ma 5 maximum input current i o 4 ma 6, 7 20 ma 6, 8 maximum output current ? o 4 ma 9, 10 30 ma 10, 11 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +125 c notes: permanent damage may occur if these absolute maximum ratings are exceeded. normal operation must be under the conditions stated in the electrical characteristics tables. if these conditions are exceeded, the lsi may malfunction or its reliability may be affected. 1. applies to pin test (v pp ) of HD4074339. 2. applies to all standard voltage pins. 3. applies to high-voltage pins. 4. the total permissible input current is the total of input currents simultaneously flowing in from all the i/o pins to gnd. 5. the total permissible output current is the total of output currents simultaneously flowing out from v cc to all i/o pins. 6. the maximum input current is the maximum current flowing from each i/o pin to gnd. 7. applies to ports r3, r4, and r5. 8. applies to ports r0, r6, and r7. 9. applies to ports r0 and r3 to r7. 10. the maximum output current is the maximum current flowing from v cc to each i/o pin. 11. applies to ports d 0 ? 13 , r1, r2, r8, and r9.
hd404339 series 68 electrical characteristics dc characteristics (v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc ?40 v to v cc , t a = ?0 to +75 c, unless otherwise specified) item symbol pins min typ max unit test condition notes input high voltage v ih reset , sck , si, int 0 , int 1 , stopc , evnb 0.8v cc ? cc + 0.3 v osc 1 v cc ?0.5 v cc + 0.3 v input low voltage v il reset , sck , si ?.3 0.2v cc v int 0 , int 1 , stopc , evnb v cc ?40 0.2v cc v osc 1 ?.3 0.5 v output high voltage v oh sck , so, toc v cc ?0.5 v i oh = 0.5 ma output low voltage v ol sck , so, toc 0.4 v i ol = 0.4 ma i/o leakage current |i il | reset , sck , si, so,toc, osc 1 1 m av in = 0 v to v cc 1 int 0 , int 1 , stopc , evnb 20 m av in = v cc ?40 to v cc 1 current dissipation in active mode i cc v cc 5.0 ma v cc = 5 v, f osc = 4 mhz 2, 5 8.0 ma 2, 6 current dissipation in standby mode i sby v cc 2.0 ma v cc = 5 v, f osc = 4 mhz 3 current dissipation in subactive mode i sub v cc 100 m av cc = 5 v, 32 khz oscillator 4, 5 320 m a 4, 6 current dissipation in watch mode i wtc v cc 20 m av cc = 5 v, 32 khz oscillator 4 current dissipation in stop mode i stop v cc 10 m a x1 = gnd, x2 = open 4, 5 20 m a 4, 6 stop mode retaining voltage v stop v cc 2 v
hd404339 series 69 notes: 1. excludes current flowing through pull-up mos and output buffers. 2. i cc is the source current when no i/o current is flowing while the mcu is in reset state. test conditions: mcu: reset pins: reset , test at gnd r0, r3 0 to r7 2 at v cc d 0 ? 13 , r1, r2, r8, r9, ra 1 at v disp 3. i sby is the source current when no i/o current is flowing while the mcu timer is operating. test conditions: mcu: i/o reset standby mode pins: reset at v cc test at gnd r0, r3 0 to r7 2 at v cc d 0 ? 13 , r1, r2, r8, r9, ra 1 at v disp 4. this is the source current when no i/o current is flowing. test conditions: pins: r0, r3 0 to r7 2 at v cc d 0 ? 13 , r1, r2, r8, r9, ra 1 at gnd 5. applies to the hd404334, hd404336, hd404338, hd4043312, and hd404339. 6. applies to the HD4074339.
hd404339 series 70 i/o characteristics for high-voltage pins (v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc ?40 v to v cc , t a = ?0 to +75 c, unless otherwise specified) item symbol pins min typ max unit test condition note input high voltage v ih d 0 ? 13 , r1, r2, r8, r9, ra 1 0.7v cc ? cc + 0.3 v input low voltage v il d 0 ? 13 , r1, r2, r8, r9, ra 1 v cc ?40 0.3v cc v output high voltage v oh d 0 ? 13 , r1, r2, r8, r9, buzz v cc ?3.0 v i oh = 15 ma v cc ?2.0 v i oh = 10 ma v cc ?1.0 v i oh = 4 ma output low voltage v ol d 0 ? 13 , r1, r2, r8, r9, buzz v cc ?37 v v disp = v cc ?40 v 1 v cc ?37 v 150 k w at v cc ?40 v 2 i/o leakage current |i il |d 0 ? 13 , r1, r2, r8, r9, ra 1 , buzz 20 m av in = v cc ?40 v to v cc 3 pull-down mos current i pd d 0 ? 13 , r1, r2, r8, r9 200 600 1000 m av disp = v cc ?35 v, v in = v cc 1 notes: 1. applies to pins with pull-down mos as selected by the mask option . 2. applies to pins without pull-down mos as selected by the mask option. 3. excludes output buffer current.
hd404339 series 71 a/d converter characteristics (v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc ?40 v to v cc , t a = ?0 to +75 c, unless otherwise specified) item symbol pins min typ max unit test condition note analog supply voltage av cc av cc v cc ?0.3 v cc v cc + 0.3 v 1 analog input voltage av in an 0 ?n 11 av ss ?v cc v current flowing between av cc and av ss i ad 200 m av cc = av cc = 5.0 v analog input capacitance ca in an 0 ?n 11 30 pf resolution 8 8 8 bit number of input channels 0 12 channel absolute accuracy 2.0 lsb conversion time 34 67 t cyc input impedance an 0 ?n 11 1 m w note: 1. connect this to v cc if the a/d converter is not used.
hd404339 series 72 ac characteristics (v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc ?40 v to v cc , t a = ?0 to +75 c) item symbol pins min typ max unit test condition note clock oscillation frequency f osc osc 1 , osc 2 0.4 4 4.5 mhz system clock divided by 4 1 x1, x2 32.768 khz instruction cycle time t cyc 0.89 1 10 m s1 t subcyc 244.14 m s 32-khz oscillator, 1/8 system clock division ratio 122.07 m s 32-khz oscillator, 1/4 system clock division ratio oscillation stabilization time (ceramic oscillator) t rc osc 1 , osc 2 7.5 ms 2 oscillation stabilization time (crystal oscillator) t rc osc 1 , osc 2 40 ms 2 x1, x2 2 s 2 external clock high width t cph osc 1 92 ns 3 external clock low width t cpl osc 1 92 ns 3 external clock rise time t cpr osc 1 20 ns 3 external clock fall time t cpf osc 1 20 ns 3 int 0 , int 1 , evnb high widths t ih int 0 , int 1 , evnb 2 t cyc / t subcyc 4 int 0 , int 1 , evnb low widths t il int 0 , int 1 , evnb 2 t cyc / t subcyc 4 reset low width t rstl reset 2 t cyc 5 stopc low width t stpl stopc 1 t rc 6 reset rise time t rstr reset 20 ms 5 stopc rise time t stpr stopc 20 ms 6 input capacitance c in all input pins except test 30 pf f = 1 mhz, v in = 0 v test 30 pf f = 1 mhz, v in = 0 v 7 180 pf 8 notes: 1. when using the subsystem oscillator (32.768 khz), one of the following relationships for f osc must be applied. 0.4 mhz f osc 1.0 mhz or 1.6 mhz f osc 4.5 mhz the operating range for f osc can be set with bit 1 of system selection register 1 (ssr1: $027). 2. the oscillation stabilization time is the period required for the oscillator to stabilize in the following situations:
hd404339 series 73 a. after v cc reaches 4.0 v at power-on. b. after reset input goes low when stop mode is cancelled. c. after stopc input goes low when stop mode is cancelled. to ensure the oscillation stabilization time at power-on or when stop mode is cancelled, reset or stopc must be input for at least a duration of t rc . when using a crystal or ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 3. refer to figure 56. 4. refer to figure 57. 5. refer to figure 58. 6. refer to figure 59. 7. applies to the hd404334, hd404336, hd404338, hd4043312, and hd404339. 8. applies to the HD4074339. serial interface timing characteristics (v cc = 4.0 to 5.5 v, gnd = 0 v, v disp = v cc ?40 v to v cc , t a = ?0 to +75 c, unless otherwise specified) during transmit clock output item symbol pins min typ max unit test condition note transmit clock cycle time t scyc sck 1t cyc load shown in figure 61 1 transmit clock high width t sckh sck 0.4 t scyc load shown in figure 61 1 transmit clock low width t sckl sck 0.4 t scyc load shown in figure 61 1 transmit clock rise time t sckr sck 80 ns load shown in figure 61 1 transmit clock fall time t sckf sck 80 ns load shown in figure 61 1 serial output data delay time t dso so 300 ns load shown in figure 61 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 during transmit clock input item symbol pins min typ max unit test condition note transmit clock cycle time t scyc sck 1 t cyc 1 transmit clock high width t sckh sck 0.4 t scyc 1 transmit clock low width t sckl sck 0.4 t scyc 1 transmit clock rise time t sckr sck 80 ns 1 transmit clock fall time t sckf sck 80 ns 1 serial output data delay time t dso so 300 ns load shown in figure 61 1 serial input data setup time t ssi si 100 ns 1 serial input data hold time t hsi si 200 ns 1 note: 1. refer to figure 60.
hd404339 series 74 t cpr t cpf v cc ?0.5 v 0.5 v osc 1 t cph t cpl 1/f cp figure 56 external clock timing 0.8v cc 0.2v cc int 0 , int 1 , evnb t ih t il figure 57 interrupt timing reset t rstr t rstl 0.2v cc 0.8v cc figure 58 reset timing t stpr t stpl 0.8v cc 0.2v cc stopc figure 59 stopc timing
hd404339 series 75 0.8v cc 0.2v cc t dso t sckf t sckl t ssi t hsi t scyc t sckr 0.8 v v ?2.0 v cc v ?2.0 v (0.8v ) * cc 0.8 v (0.2v ) * sck so si note: * v cc ?2.0 v and 0.8 v are the threshold voltages for transmit clock output, and 0.8v cc and 0.2v cc are the threshold voltages for transmit clock input. cc cc t sckh figure 60 serial interface timing r l = 2.6 k w v cc hitachi 1s2074 or equivalent r = 12 k w test point c = 30 pf figure 61 timing load circuit
hd404339 series 76 notes on rom out please pay attention to the following items regarding rom out. on rom out, fill the rom area indicated below with 1s to create the same data size for the hd404334 and hd404336 as an 8-kword version (hd404338), and to create the same data size for t he hd4043312 as a 16-kword version (hd404339). the 8-kword and 16-kword data sizes are required to change rom data to mask manufacturing data since the program used is for an 8-k or 16-kword version. this limitation applies when using an eprom or a data base. vector address zero-page subroutine (64 words) pattern & program (4,096 words) not used vector address zero-page subroutine (64 words) pattern & program (6,144 words) not used rom 4-kword version: hd404334 address $1000?1fff rom 6-kword version: hd404336 address $1800?1fff $0000 $000f $0010 $003f $0040 $0fff $1000 $1fff $0000 $000f $0010 $003f $0040 $17ff $1800 $1fff fill this area with 1s vector address zero-page subroutine (64 words) pattern & program (12,288 words) not used rom 12-kword version: hd4043312 address $3000?3fff $0000 $000f $0010 $003f $0040 $2fff $3000 $3fff
hd404339 series 77 hd404334/hd404336/hd404338/hd4043312/hd404339 option list 5. rom code media eprom: ceramic oscillator crystal oscillator external clock f = mhz f = mhz f = mhz 6. system oscillator (osc1, osc2) ra1 without pull-down resistance vdisp 4. ra1/vdisp note: if even only one pin is selected with i/o option e, pin ra1/vdisp must be selected to function as vdisp. with 32-khz cpu operation, with time base for clock without 32-khz cpu operation, with time base for clock without 32-khz cpu operation, without time base * * 2. optional functions 3. i/o options note: * options marked with an asterisk require a subsystem crystal oscillator (x1, x2). the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu...). eprom: the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. fp-64b dp-64s 8. package please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat version). used not used 7. stop mode date of order customer department name rom code name lsi number hd404334 hd404336 hd404338 hd4043312 hd404339 1. rom size 4-kword 6-kword 8-kword 12-kword 16-kword d0/ int 0 d1/ int 1 d2/evnb d3/buzz d4/ stopc d5 d6 d7 d8 d9 d10 d11 d12 d13 pin name i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o option de d: without pull-down resistance r1 r2 r8 r9 r10 r11 r12 r13 r20 r21 r22 r23 r80 r81 r82 r83 r90 r91 r92 r93 pin name i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o option de e: with pull-down resistance please check off the appropriate applications and enter the necessary information.
hd404339 series 78 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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